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cy7c65215 usb-serial dual channel (uart/i 2 c/spi) bridge with capsense ? and bcd cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-81006 rev. *g revised february 21, 2014 features usb 2.0 certified, full-speed (12 mbps) ? support for communication driver class (cdc), personal health care device class (phdc), and vendor specific drivers ? battery charger detection (bcd) compliant with usb battery charging specification rev 1.2 (peripheral detect only) ? integrated usb termination resistors two-channel configurable uart interfaces ? data rates up to 3 mbps ? 256 bytes each transmit and receive buffer per channel ? data format:] ? 7 to 8 data bits ? 1 to 2 stop bits ? no parity, even, odd, mark, or space parity ? supports parity, overrun, and framing errors ? supports flow control using cts, rts, dtr, dsr two-channel configurable spi interfaces ? master/slave up to 3 mhz ? data width: 4 bits to 16 bits ? 256 bytes for each transmit and receive buffer per channel ? supports motorola, ti, and national spi modes two-channel configurable i 2 c interfaces ? master/slave up to 400 khz ? supports multi-master i 2 c ? 256 bytes for each transmit and receive buffer per channel capsense ? ? smartsense? auto-tuning is supported through a cypress-supplied configuration utility ? max capsense buttons: 8 ? gpios linked to capsense buttons jtag interface: jtag master for code flashing at 400 khz general-purpose input/o utput (gpio) pins: 17 configuration utility (windows) to configure the following: ? vendor id (vid), product id (pid), and product and manu- facturer descriptors ? uart/i 2 c/spi/jtag ? capsense ? charger detection ? gpio driver support for vcom and dll ? windows 8: 32- and 64-bit versions ? windows 7: 32- and 64-bit versions ? windows vista: 32- and 64-bit versions ? windows xp: 32- and 64-bit versions ? windows ce ? mac os-x: 10.6, 10.7 ? linux: kernel version 2.6.35 onwards ? android: gingerbread and later versions clocking: integrated 48 -mhz clock oscillator supports bus-/self-powered configurations usb suspend mode for low power operating voltage: 1.71 to 5.5 v operating temperature: ?40 ? c to 85 ? c esd protection: 2.2 kv hbm rohs compliant package ? 32-pin qfn (5 5 1 mm. 0.5 mm pitch) ordering part number ? CY7C65215-32LTXI applications medical/healthcare devices point-of-sale (pos) terminals test and measurement system gaming systems set-top box pc-usb interface industrial networking enabling usb connectivity in legacy peripherals usb compliant the usb-serial dual-channel bridge with capsense an d bcd (cy7c65215) is fully compliant with the usb 2.0 specification and battery charging sp ecification v1.2, usb-if test-id (tid) 40001521.
cy7c65215 document number: 001-81006 rev. *g page 2 of 31 contents block diagram .................................................................. 3 functional overview ........................................................ 3 usb and charger detect ............................................. 3 serial communication ................................................. 3 capsense .................................................................... 4 jtag interface ............................................................ 4 gpio interface ............................................................ 4 memory ....................................................................... 4 system resources ...................................................... 4 suspend and resume ................................................. 4 wakeup ..................................................................... 5 software ...................................................................... 5 internal flash configuration ........................................ 6 electrical specifications .................................................. 7 absolute maximum ratings .... ..................................... 7 operating conditions ................................................... 7 device level specifications ......................................... 7 gpio ........................................................................... 8 nxres ......................................................................... 9 spi specifications ..................................................... 10 i2c specifications ...................................................... 12 jtag specifications .................................................. 12 capsense specifications .......................................... 12 flash memory specifications .................................... 12 pin description ............................................................... 13 usb power configurations ............................................ 16 usb bus-powered configuration .............................. 16 self powered configuration ....................................... 17 usb bus powered with variable i/o voltage ............ 18 application examples .................................................... 19 usb-to-dual uart bridge with battery-charge detection .......................................... 19 capsense .................................................................. 21 usb-to-dual channel (i2c/spi ) bridge .... ............ ..... 22 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package information ...................................................... 28 acronyms ........................................................................ 29 document conventions ................................................. 29 units of measure ....................................................... 29 document history page ................................................. 30 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc? solutions ...................................................... 31 cypress developer community ................................. 31 technical support ................. .................................... 31
cy7c65215 document number: 001-81006 rev. *g page 3 of 31 block diagram functional overview the cy7c65215 is a full-speed usb controller that enables seamless pc connectivity for peripherals with dual-channel serial interfaces such as uart, spi, and i 2 c. cy7c65215 also integrates capsense and bcd, wh ich is compliant with the usb battery charging specification rev. 1.2. it integrates a voltage regulator, oscillator, and flash me mory for storing configuration parameters, offering a cost-effective solution. cy7c65215 supports bus-powered and self-powered modes, and enables efficient system power management with suspend and remote wake-up signals. it is available in a 32-pin qfn package. usb and charger detect usb cy7c65215 has a built-in usb 2 . 0 full-speed transceiver. the transceiver incorporates the internal usb series termination resistors on the usb data lines and a 1.5-k ? pull - up resistor on usbdp. charger detection cy7c65215 supports bcd for peripheral detect only and complies with the usb battery charging specification rev . 1.2 . it supports the following charging ports: standard downstream port (sdp): allows the system to draw up to 500 ma current from the host charging downstream port (cdp): allows the system to draw up to 1.5 a current from the host dedicated charging port (dcp): allows the system to draw up to 1.5 a of current from the wall charger serial communication cy7c65215 has two serial communication blocks (scbs) . each scb can implement uart, spi, or an i 2 c interface. a 256-byte buffer is available in both the tx and rx lines. uart interface the uart interface provides asynchronous serial communi- cation with other uart devices operating at speeds of up to 3 mbps. it supports 7 to 8 data bits, 1 to 2 stop bits, odd, even, mark, space, and no parity. the uart interface supports full duplex communication with a signaling format that is compatible with the standard uart protocol. the uart pins may be inter- faced to industry-standard rs-232 transceivers to manage different voltage levels. cy7c65215 supports common uart functions such as parity error and frame error. in addition, cy7c65215 supports baud rates ranging from 300 baud to 3 mbaud. uart baud rates can be set using the configuration utility. uart flow control the cy7c65215 device supports uart hardware flow control using control signal pairs such as rts# (request to send) / cts# (clear to send) and dtr# (data terminal ready) / dsr# (data set ready). data flow control is enabled by default. flow control can be disabled usi ng the configur ation utility. the following section describes the flow control signals: cts# (input) / rts# (output) cts# can pause or resume dat a transmission over the uart interface. data transmission can be paused by de-asserting the cts signal and resumed with cts# assertion. the pause and resume operation does not affect data integrity. the receive buffer has a watermark level of 80%. after the data in the receive buffer reaches that level, the rts# signal is de-asserted, instructing the transmitting devic e to stop data transmission. the start of data consumption by the application reduces device data backlog. when it reaches the 50% watermark level, the rts# signal is asserted to resume data reception. dsr# (input) /dtr# (output) dsr#/dtr# signals are used to establish the communication link with the uart. these signals complement each other in their functionality, similar to cts# and rts#. usb transceiver with integrated resistor voltage regulator internal 48 mhz osc gpio capsense usbdp usbdm battery charger detection sie usb internal 32 khz osc reset scb 0 uart/ spi/i 2 c 256 bytes rx buffer 256 bytes tx buffer scb 1 uart/ spi/i 2 c 256 bytes rx buffer 256 bytes tx buffer nxres vddd vbus vccd gnd 512 bytes flash memory vbus regulator channel 0 uart/spi/i 2 c channel 1 uart/spi/i 2 c gpio capsense jtag jtag (master)
cy7c65215 document number: 001-81006 rev. *g page 4 of 31 spi interface the spi interface supports spi master and spi slave. this interface supports the motorola, ti, and national microwire protocols. the maximum frequency of operation is 3 mhz in the master and slave modes. it can support transaction sizes ranging from 4 bits to 16 bits in length (for more details, refer to usb-to-dual channel (i2c/spi) bridge on page 22 ). i 2 c interface the i 2 c interface implements full multi-master/slave modes and supports up to 400 khz. the configuration utility tool is used to set the i 2 c address in slave mode. this tool enables only even slave addresses. for further details on protocol, refer to the nxp i 2 c specification rev5. notes i 2 c ports are not tolerant of higher voltages and cannot be hot-swapped or powered up independe ntly from the rest of the i 2 c system. the minimum fall time is not met, as required by the nxp i 2 c specification rev5, except when v ddd = 1.71 v to 3.0 v. the minimum fall time can be met by adding a 50-pf capacitor for the v ddd = 3.0 v?3.6 v range. capsense capsense functionality is supported on all the gpio pins. any gpio pin can be configured as a sense pin (cs0?cs7) using the configuration utility. when implem enting capsense functionality, the gpio_0 pin (configured as t he modulator capacitor - cmod) should be connected to ground through a 2.2-nf capacitor (see figure 10 on page 21 ). cy7c65215 supports smartsense auto-tuning of capsense parameters and does not require manual tuning. smartsense au to-tuning compensates for printed circuit board (pcb) variations and device process varia- tions. optionally, any gpio pin can be configured as a cshield and connected to the shield of the capsense button as shown in figure 10 on page 21 . the shield prevents false triggering of buttons due to water droplets and guarantees capsense operation (sensors respond to finger touch). gpios can be linked to capsense buttons to indicate the presence of a finger. capsense functionality can be configured using configuration utility. cy7c65215 supports up to eight capsense buttons. for more information on capsense, refer to getting started with capsense . jtag interface cy7c65215 supports a 5-pin jtag in master mode for code flashing at 400 khz. gpio interface cy7c65215 has 17 gpios. a maximum of 17 gpios are available for configuration if one 2-pin (i 2 c/2-pin uart) serial interface is implemented. the conf iguration utility allows config- uration of the gpio pins. the configurable options are as follows: tristate: gpio tristated drive 1: output static 1 drive 0: output static 0 power#: power control for bus power designs txled#: drives led during usb transmit rxled#: drives led during usb receive tx or rx led#: drives led during usb transmit or receive gpio can be configured to driv e led at 8-ma drive strength. bcd0/bcd1: two-pin output to indicate the type of usb charger busdetect: connects vbus pin for usb host detection cs0?cs7: capsense button input (sense pin) csout0?csout3: indicates which capsense button is pressed cmod: external modulator capacitor that connects a 2.2-nf capacitor (10%) to ground (gpio_0 only) cshield: shield for waterproofing memory cy7c65215 has a 512-byte flash. the flash is used to store the usb parameters such as vid/pid, serial number, product, and manufacturer descriptors, which can be programmed by the configuration utility. system resources power system cy7c65215 supports the usb suspend mode to control power usage. cy7c65215 operates in bus-powered or self-powered modes over a range of 3.15 to 5.25 v. clock system cy7c65215 has a fully integrated clock and does not require any external components. the clock system is responsible for providing clocks to all subsystems. internal 48-mhz oscillator the internal 48-mhz oscillator is the primary source of internal clocking in cy7c65215. internal 32-khz oscillator the internal 32-khz oscillator is low power and relatively inaccurate. it is primarily used to generate clocks for peripheral operation in the usb suspend mode. reset the reset block ensures reliable power-on reset or reconfigu- ration to a known state. the nxres (active low) pin can be used by external devices to reset the cy7c65215. suspend and resume the cy7c65215 device asserts the suspend pin when the usb bus enters the suspend state. this helps in meeting the stringent suspend current requir ement of the usb 2.0 specifi- cation, while using the device in bus-powered mode. the device will resume from the suspend state under any of the following conditions: 1. any activity is detected on the usb bus
cy7c65215 document number: 001-81006 rev. *g page 5 of 31 2. the wakeup pin is asserted to generate remote wakeup to the host wakeup the wakeup pin is used to generate a remote wakeup signal on the usb bus. the remote wakeup signal is sent only if the host enables this feature through the set_feature request. the device communicates support for the remote wakeup to the host through the configuration descriptor during the usb enumeration process. the cy7c65215 device allows enabling/disabling and polarity of the remote wakeup feature through the configuration utility. software cypress delivers a complete set of software drivers and the configuration utility to enabl e product configuration during system development. drivers for linux operating systems cypress provides a user mode usb driver library ( libcyusb- serial.so ) that abstracts vendor commands for the uart interface and provides a simplified api interface to the user appli- cations. this library makes use of the standard open source libusb library to enable the usb communication. the cypress serial library supports the usb plug-and-play feature using the linux 'udev' mechanism. cy7c65215 supports the standard usb cdc uart class driver, which is bundled with the linux kernel. android support the cy7c65215 solution includes an android java class?cyusbserial.java?which exposes a set of interface functions to communicate with the device. drivers for mac osx cypress delivers a dynamically linked shared library (cyusb- serial.dylib) based on libusb, which enables communication to the cy7c65215 device. in addition, the device also supports the native mac osx cdc uart-class driver. drivers for windows operating systems for windows operating systems (xp, vista, win7, and win8), cypress delivers a user mode dynamically linked library?cyusbserial dll?that abstracts vendor-specific interface of cy7c65215 devices and provides convenient apis to the user. it provides interface apis for vendor-specific uart and class-specific apis for phdc. a virtual com port driver ? cyu sbserial.sys ? is also delivered, which implements the usb cdc class driver. the cypress windows drivers are: windows driver foundation (wdf) compliant compatible with any usb 2.0-compliant device compatible with cypress usb 3.0-compliant devices they also support windows plug-and-play and power management and usb remote wake-up cy7c65215 also works with the windows-standard usb cdc uart class driver. windows-ce support the cy7c65215 solution also includes a dynamically linked library (dll) and cdc uart driver library for windows-ce platforms. device configuration utility (windows only) a windows-based configuration uti lity is available to configure various device initialization parameters. this graphical user application provides an interactive interface to define the various boot parameters stored in the device flash. this utility allows the user to save a user-selected configuration to text or xml formats. it also allows users to load a selected configuration from text or xml formats. the configuration utility allows the following operations: view current device configuration select and configure uart/i2c/spi, capsense, battery charging, and gpios configure usb vid, pid, and string descriptors save or load configuration you can download the free configur ation utility and drivers from www.cypress.com .
cy7c65215 document number: 001-81006 rev. *g page 6 of 31 internal flash configuration the internal flash memory can be used to st ore the configuration parameters shown in the following table. a free configuration utility is provided to configure the parameters listed in the table to m eet application specific requirem ents over usb interface. the c onfigu- ration utility can be downloaded from www.cypress.com. table 1. internal flash configuration parameter default value description usb configuration usb vendor id (vid) 0x04b4 default cypress vi d. can be configured to customer vid usb product id (pid) 0x0005 default cypress pi d. can be configured to customer pid manufacturer string cypress can be configured with any string up to 64 characters product string usb-serial (dual channel) can be configured with any string up to 64 characters serial string can be configured with any string up to 64 characters power mode bus powered can be configured to bus-powered or self-powered mode max current draw 100 ma can be configured to any valu e from 0 to 500 ma. based on this, the config- uration descriptor will be updated. remote wakeup en abled can be disabled . remote wakeup is initia ted by asserting wakeup pin usb interface protocol cdc can be configured to function in cdc, phdc, or cypress vendor class bcd disabled charger detect is disabled by default. when bcd is enabled, three of the gpios must be configured for bcd gpio configuration gpio_0 txled# gpio can be configured as shown in table 16 on page 15 . gpio_1 rxled# gpio_2 dsr#_0 gpio_3 rts#_0 gpio_4 cts#_0 gpio_5 txd_0 gpio_6 power# gpio_7 tristate gpio_8 rxd_0 gpio_9 dtr#_0 gpio_10 rxd_1 gpio_11 txd_1 gpio_12 rts#_1 gpio_13 cts#1 gpio_14 dsr#_1 gpio_15 dtr#_1 gpio_16 tristate gpio_17 tristate gpio_18 tristate
cy7c65215 document number: 001-81006 rev. *g page 7 of 31 electrical specifications absolute maximum ratings exceeding maximum ratings [1] may shorten the useful life of the device. storage temperature .............................. ...... ?55 c to +100 c ambient temperature with power supplied (industri al) ...................... ...... ?40 c to +85 c supply voltage to ground potential v ddd .................................................................................. 6.0 v v bus .................................................................................. 6.0 v v ccd ................................................................................1.95 v v gpio ........................................................................v ddd + 0.5 static discharge voltage esd protection levels: 2.2-kv hbm per jesd22-a114 latch-up current ........................................................... 140 ma current per gpio ........................................................... 25 ma operating conditions t a (ambient temperature under bias) industrial ........................................................ ?40 c to +85 c v bus supply voltage ......... .............. ............... .. 3.15 v to 5.25 v v ddd supply voltage ........................................ 1.71 v to 5.50 v v ccd supply voltage ........................................ 1.71 v to 1.89 v device level specifications all specifications are valid for ?40 c ? t a ? 85 c, t j ? 100 c, and 1.71 v to 5.50 v, except where noted. table 2. dc specifications parameter description min typ max units details/conditions v bus v bus supply voltage 3.15 3.30 3.45 v set and configure correct voltage range using the configuration utility for v bus . default 5 v. 4.35 5.00 5.25 v v ddd v ddd supply voltage 1.71 1.80 1.89 v used to set i/o and core voltage. set and configure correct voltage range using the configuration utility for v ddd . default 3.3 v. 2.0 3.3 5.5 v v ccd output voltage (for core logic) ? 1.8 0 ? v do not use this supply to drive external device. ?1.71v ? v ddd ?? 1.89 v: short the v ccd pin with the v ddd pin ?v ddd > 2 v ? connect a 1-f capacitor (cefc) between the v ccd pin and ground cefc external regulator voltage bypass 1.00 1.30 1.60 f x5r ceramic or better i dd1 operating supply current ? 20 ? ma usb 2.0 fs, uart at 1 mbps single channel, no gpio switching i dd2 usb suspend supply current ? 5 ? a does not include current through a pull-up resistor on usbdp table 3. ac specifications parameter description min typ max units details/conditions f1 frequency 47.04 48 48.96 mhz non-usb mode f2 47.88 48 48.12 usb mode zout usb driver output impedance 28 ? 44 ? twakeup wakeup from usb suspend mode ? 25 ? s note 1. usage above the absolute maximum conditions may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods of time may affect device reliability. when used below absolute maximum conditions but above normal operating conditions the devic e may not operate to specification.
cy7c65215 document number: 001-81006 rev. *g page 8 of 31 gpio table 4. gpio dc specification parameter description min typ max units details/conditions v ih [2] input voltage high threshold 0.7 v ddd ? ? v cmos input v il input voltage low threshold ? ? 0.3 v ddd v cmos input v ih [2] lvttl input, v ddd < 2.7 v 0.7 v ddd ? ? v v il lvttl input, v ddd < 2.7 v ? ? 0.3 v ddd v v ih [2] lvttl input, v ddd > 2.7 v 2 ? ? v v il lvttl input, v ddd > 2.7 v ? ? 0.8 v v oh output voltage high level v ddd ?0.4 ? ? v i oh = 4 ma, v ddd = 5 v +/- 10% v oh output voltage high level v ddd ?0.6 ? ? v i oh = 4 ma, v ddd = 3.3 v +/- 10% v oh output voltage high level v ddd ?0.5 ? ? v i oh = 1 ma, v ddd = 1.8 v +/- 5% v ol output voltage low level ? ? 0.4 v i ol = 8 ma, v ddd = 5 v +/- 10% v ol output voltage low level ? ? 0.6 v i ol = 8 ma, v ddd = 3.3 v +/- 10% v ol output voltage low level ? ? 0.6 v i ol = 4 ma, v ddd = 1.8 v +/- 5% rpullup pull-up resistor 3.5 5.6 8.5 k ? rpulldown pull-down resistor 3.5 5.6 8.5 k ? i il input leakage current (absolute value) ? ? 2 na 25 c, v ddd = 3.0 v c in input capacitance ? ? 7 pf vhysttl input hysteresis lvttl; v ddd > 2.7 v 25 40 ? mv vhyscmos input hysteresis cmos 0.05 v ddd ?? mv table 5. gpio ac specification parameter description min typ max units details/conditions t risefast1 rise time in fast mode 2 ? 12 ns v ddd = 3.3 v/ 5.5 v, cload = 25 pf t fallfast1 fall time in fast mode 2 ? 12 ns v ddd = 3.3 v/ 5.5 v, cload = 25 pf t riseslow1 rise time in slow mode 10 ? 60 ns v ddd = 3.3 v/ 5.5 v, cload = 25 pf t fallslow1 fall time in slow mode 10 ? 60 ns v ddd = 3.3 v/ 5.5 v, cload = 25 pf t risefast2 rise time in fast mode 2 ? 20 ns v ddd = 1.8 v, cload = 25 pf t fallfast2 fall time in fast mode 20 ? 100 ns v ddd = 1.8 v, cload = 25 pf t riseslow2 rise time in slow mode 2 ? 20 ns v ddd = 1.8 v, cload = 25 pf t fallslow2 fall time in slow mode 20 ? 100 ns v ddd = 1.8 v, cload = 25 pf note 2. v ih must not exceed v ddd + 0.2 v.
cy7c65215 document number: 001-81006 rev. *g page 9 of 31 nxres table 6. nxres dc specifications parameter description min typ max units details/conditions v ih input voltage high threshold 0.7 v ddd ?? v v il input voltage low threshold ? ? 0.3 v ddd v rpullup pull-up resistor 3.5 5.6 8.5 k ? c in input capacitance ? 5 ? pf vhysxres input voltage hysteresis ? 100 ? mv table 7. nxres ac specifications parameter description min typ max units details/conditions tresetwidth reset pulse width 1 ? ? s table 8. uart ac specifications parameter description min typ max units details/conditions f uart uart bit rate 0.3 ? 3000 kbps single scb: tx + rx dual scb: tx or rx
cy7c65215 document number: 001-81006 rev. *g page 10 of 31 spi specifications figure 1. spi master timing lsb lsb msb msb lsb msb f spi t dmo t dsi sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) spi master timing for cpha = 0 (refer to table 17) spi master timing for cpha = 1 (refer to table 17) t hmo f spi t dsi t dmo t hmo lsb msb
cy7c65215 document number: 001-81006 rev. *g page 11 of 31 figure 2. spi slave timing lsb lsb msb msb lsb lsb msb msb t sselsck t dmi t dso ssn (input) sck (cpol=0, input) sck (cpol=1, input) miso (output) mosi (input) ssn (input) sck (cpol=0, input) sck (cpol=1, input) miso (ouput) mosi (input) spi slave timing for cpha = 0 (refer to table 17) spi slave timing for cpha = 1 (refer to table 17) t sselsck f spi f spi t hso t dmi t dso t hso
cy7c65215 document number: 001-81006 rev. *g page 12 of 31 i 2 c specifications jtag specifications capsense specifications flash memory specifications table 9. spi ac specifications parameter description min typ max units details/conditions f spi spi operating frequency (master/slave) ? ? 3 mhz single scb: tx + rx dual scb: tx or rx wl spi spi word length 4 ? 16 bits spi master mode t dmo mosi valid after sclock driving edge ? ? 15 ns t dsi miso valid before sclock capturing edge 2 0 ?? ns t hmo previous mosi data hold time with respect to capturing edge at slave 0?? ns spi slave mode t dmi mosi valid before sclock capturing edge 4 0 ? ? ns t dso miso valid after sclock driving edge ? ? 104.4 ns t hso previous miso data hold time 0 ? ? ns t sselsck ssel valid to first sck valid edge 100 ? ? ns table 10. i 2 c ac specifications parameter description min typ max units details/conditions f i2c i 2 c frequency 1 ? 400 khz table 11. jtag ac specifications parameter description min typ max units details/conditions f jtag jtag operating frequency (master) ? ? 400 khz code flashing table 12. capsense ac specifications parameter description min typ max units details/conditions v csd voltage range of operation 1.71 ? 5.50 v snr ratio of counts of finger to noise 5 ? ? ratio sensor capacitance range of 9 to 35 pf; finger capacitance > = 0.1 pf sensitivity table 13. flash memory specifications parameter description min typ max units details/conditions fend flash endurance 100 k ? ? cycles fret flash retention. t a ? 85 c, 10 k program/erase cycles 10 ? ? years
cy7c65215 document number: 001-81006 rev. *g page 13 of 31 pin description pin [3] type name default description 1power vddd ? supply to the devi ce core and interface, 1.71 to 5.5 v 2scb/gpio scb0_0 gpio_8 rxd_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 3scb/gpio scb0_5 gpio_9 dtr#_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 4 power vssd ? digital ground 5scb/gpio scb1_0 gpio_10 rxd_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 6scb/gpio scb1_1 gpio_11 txd_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 7scb/gpio scb1_2 gpio_12 rts#_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 8scb/gpio scb1_3 gpio_13 cts#_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 9scb/gpio scb1_4 gpio_14 dsr#_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 10 scb/gpio scb1_5 gpio_15 dtr#_1 gpio/scb1. see ta b l e 1 5 and table 16 on page 15 11 output suspend ? indicates device in su spend mode. can be configured as active low/high using configuration utility 12 input wakeup ? wakeup device from su spend mode. can be configured as active low/high using configuration utility 13 gpio gpio_16 tristate gpio. see table 16 on page 15 14 usbio usbdp ? usb data signal plus, integrates termination resistor and 1.5-k ? pull up resistor 15 usbio usbdm ? usb data signal minus, integrates termination resistor 16 power vccd ? regulated supply, connect to 1-f cap or 1.8 v 17 power vssd ? digital ground 18 nxres nxres ? chip reset, active low. can be left unconnected or have a pull-up resistor connected if not used. 19 power vbus ? vbus supply, 3.15 v to 5.25 v 20 power vssd ? digital ground 21 gpio gpio_17 tristate gpio. see table 16 on page 15 22 gpio gpio_18 tristate gpio. see table 16 on page 15 23 power vddd ? supply to the devi ce core and interface, 1.71 to 5.5 v 24 power vssa ? analog ground 25 gpio gpio_0 txled# gpio. see table 16 on page 15 26 gpio gpio_1 rxled# gpio. see table 16 on page 15 27 scb/gpio scb0_1 gpio_2 dsr#_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 28 scb/gpio scb0_2 gpio_3 rts#_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 29 scb/gpio scb0_3 gpio_4 cts#_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 30 scb/gpio scb0_4 gpio_5 txd_0 gpio/scb0. see ta b l e 1 4 and table 16 on page 15 31 gpio gpio_6 power# gpio. see table 16 on page 15 32 gpio gpio_7 tristate gpio. see table 16 on page 15 note 3. any pin acting as an input pin should not be left unconnected.
cy7c65215 document number: 001-81006 rev. *g page 14 of 31 figure 3. 32-pin qfn pinout cy7c65215 -32qfn top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 32 23 22 21 20 19 18 17 24 vddd scb0_0/ gpio_8 scb0_5/ gpio_9 vssd scb1_0/ gpio_10 scb1_1/ gpio_11 scb1_2/ gpio_12 scb1_3/ gpio_13 vssa vddd gpio_18 gpio_17 vssd vbus nxres vssd scb1_4/gpio_14 scb1_5/gpio_15 suspend wakeup gpio usbdp usbdm vccd gpio_7 gpio_6 scb0_4/gpio_5 scb0_3/gpio_4 scb0_2/gpio_3 scb0_1/gpio_2 gpio gpio _0 _1 _ 16 table 14. serial communicati on block (scb0) configuration pin serial port 0 mode 0* mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 6-pin uart 4-pin uart 2-pin uart spi master spi slave i 2 c master i 2 c slave 2 scb0_0 rxd_0 rxd_0 rxd_0 gpio_8 gpio_8 gpio_8 gpio_8 27 scb0_1 dsr#_0 gpio_2 gpio_2 ssel_out_0 ssel_in_0 gpio_2 gpio_2 28 scb0_2 rts#_0 rts#_0 gpio_3 miso_in_0 miso_out_0 scl_out_0 scl_in_0 29 scb0_3 cts#_0 cts#_0 gpio_4 mosi_out_0 mosi_in_0 sda_0 sda_0 30 scb0_4 txd_0 txd_0 txd_0 sclk_out_0 sclk_in_0 gpio_5 gpio_5 3 scb0_5 dtr#_0 gpio_9 gpio_9 gpio_9 gpio_9 gpio_9 gpio_9 * note : device configured in mode 0 as default. other modes c an be configured through cypress-supplied configuration utility. table 15. serial communicati on block (scb1) configuration pin serial port 1 mode 0* mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 6-pin uart 4-pin uart 2-pin uart spi master spi slave i 2 c master i 2 c slave jtag master 5 scb1_0 rxd_1 rxd_1 rxd_1 miso_in_1 miso_out_1 scl_out_1 scl_in_1 tdi 6 scb1_1 txd_1 txd_1 txd_1 mosi_out_1 mosi_in_1 sda_1 sda_1 tdo 7 scb1_2 rts#_1 rts#_1 gpio_12 ssel_out_1 ssel_in_1 gpio_12 gpio_12 tms 8 scb1_3 cts#_1 cts#_1 gpio_13 sclk_out_1 sclk_in_1 gpio_13 gpio_13 tck 9 scb1_4 dsr#_1 gpio_14 gpio_14 gpio_14 gpio_14 gpio_14 gpio_14 trst# 10 scb1_5 dtr#_1 gpio_15 gpio_15 gpio_15 gpio_15 gpio_15 gpio_15 gpio_15 * note : device configured in mode 0 as default. other modes can be configured via cypress-supplied configuration utility. gpio scb0 scb1
cy7c65215 document number: 001-81006 rev. *g page 15 of 31 table 16. gpio configuration gpio configuration option description tristate i/o tristated drive 1 output static 1 drive 0 output static 0 power# this output is used to control power to an external logic via switch to cut power off during unconfigured usb device and usb suspend. 0 - usb device in configured state 1 - usb device in unconfigured state or during usb suspend mode txled# drives led during usb transmit rxled# drives led during usb receive tx or rx led# drives led during usb transmit or receive bcd0 bcd1 configurable battery charger detect pins to indicate type of usb charger (sdp, cdp, or dcp) configuration example: 00 - draw up to 100 ma (unconfigured state) 01 - sdp (up to 500 ma) 10 - cdp/dcp (up to 1.5 a) 11 - suspend (up to 2.5 ma) this truth table can be configured using the config uration utility busdetect vbus detection. connect vbus to this pi n via resistor network for vbus detection when using bcd feature (refer to page 20). cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 capsense button input (max up to 8) csout0, csout1, csout2, csout3 indicates which capsense button is pressed cmod (available on gpio_0 only) external modulator capacitor, connect a 2.2 nf capacitor (10%) to ground cshield (optional) shield for waterproofing note: these signal options can be configured on any of the available gpio pins us ing cypress-supplied configuration utility.
cy7c65215 document number: 001-81006 rev. *g page 16 of 31 usb power configurations the following section describes possible usb power configurations for the cy7c65215. refer to the pin description on page 13 for signal details. usb bus-powered configuration figure 4 shows an example of the cy7c65215 in a bus-powered design. vbus is connected directly to the cy7c65215 because it has an internal regulator. the usb bus-powered system must comply with the following requirements: 1. the system should not draw more than 100 ma prior to usb enumeration (unconfigured state). 2. the system should not draw mo re than 2.5 ma during usb suspend mode. 3. a high-power bus- powered system (can draw more than 100 ma when operational) must use power# (configured over gpio) to keep the current consumption below 100 ma prior to usb enumeration, and 2.5 ma during usb suspend state. 4. the system should not draw mo re than 500 ma from the usb host. the configuration descriptor in the cy7c65215 flash should be updated to indicate bus power and the maximum current required by the system using the configurat ion utility. figure 4. bus powered configuration usb connector vbus d+ d- gnd vbus vccd 1 uf 0.1 uf cy7c65215 usbdp usbdm vssd nxres vddd suspend wakeup gpio_0 gpio_1 gpio_2 / scb0_1 gpio_3 / scb0_2 gpio_4 / scb0_3 gpio_9 / scb0_5 vssa gpio_15 / scb1_5 gpio_16 gpio_5 / scb0_4 gpio_6 gpio_7 gpio_8 / scb0_0 19 1 18 14 15 16 4 24 11 29 27 vssd vssd 17 20 10 28 12 3 32 2 13 31 30 25 26 gpio_10 / scb1_0 gpio_11 / scb1_1 gpio_12 / scb1_2 gpio_13 / scb1_3 gpio_14 / scb1_4 7 6 8 8 gpio_17 21 gpio_18 22 5
cy7c65215 document number: 001-81006 rev. *g page 17 of 31 self powered configuration figure 5 shows an example of cy7c65215 in a self-powered design. a self-powered system does not use vbus from the host to power the system but ha s its own power supply. a self-powered system has no rest riction on curr ent consumption because it does not draw any current from the vbus. when vbus is present, cy7c65215 enables an internal, 1.5-k ? pull-up resistor on usbdp. when vbus is absent (usb host is powered down), cy7c65215 removes the 1.5-k ? pull-up resistor on usbdp, and this ensures no current flows from the usbdp to the usb host via a 1.5-k ? pull-up resistor, to comply with usb 2.0 specification. when reset is asserted to cy7c65215, all the i/o pins are tristated. using the configuration utility, th e configuration descriptor in the cy7c65213 flash should be updated to indicate that it is self-powered. figure 5. self powered configuration usb connector vbus d+ d- gnd 0.1 uf 1.71 to 1.89 v or 2.00 to 5.50 v 3.15 to 3.45 v or 4.35 to 5.25 v vbus vccd 1 uf cy7c65215 usbdp usbdm vssd nxres vddd suspend wakeup gpio_0 gpio_1 gpio_2 / scb0_1 gpio_3 / scb0_2 gpio_4 / scb0_3 gpio_9 / scb0_5 vssa gpio_15 / scb1_5 gpio_16 gpio_5 / scb0_4 gpio_6 gpio_7 gpio_8 / scb0_0 19 1 18 14 15 16 4 24 11 29 27 vssd vssd 17 20 10 28 12 3 32 2 13 31 30 25 26 gpio_10 / scb1_0 gpio_11 / scb1_1 gpio_12 / scb1_2 gpio_13 / scb1_3 gpio_14 / scb1_4 7 6 8 8 gpio_17 21 gpio_18 22 5 10k 4.7k
cy7c65215 document number: 001-81006 rev. *g page 18 of 31 usb bus powered with variable i/o voltage figure 6 shows cy7c65215 in a bus-powered system with variable i/o voltage. a low dropout (ldo) regulator is used to supply 1.8 v or 3.3 v (using a ju mper switch) the input of which is 5 v from vbus. another jumper switch is used to select 1.8/3.3 v or 5 v from vbus for the vddd pin of cy7c65215. this allows i/o voltage and supply to external logic to be selected among 1.8 v, 3.3 v, or 5 v. the usb bus-powered system must comply with the following: the system should not draw more than 100 ma prior to usb enumeration (unconfigured state). the system should not draw more than 2.5 ma during usb suspend mode. a high-power bus-powered system (can draw more than 100 ma when operational) must use power# (configured over gpio) to keep the current consumption below 100 ma prior to usb enumeration and 2.5 ma during usb suspend state. figure 6. usb bus powered with 1.8 v, 3.3 v, or 5 v variable i/o voltage [4] usb connector vbus d+ d- gnd 0.1uf vin gnd shdn vout vadj jumper to select 1.8 v or 3.3 v vbus 0.1 uf tc 1070 1uf 1m 1 2 3 562k 2m 3.3 v 1.8 v 1 2 3 1.8/3.3 v 1.8/3.3 v 1.8 v or 3.3 v or 5 v supply to external logic jumper to select 1.8 v/3.3 v or 5 v power switch power# vbus vccd 1 uf cy7c65215 usbdp usbdm vssd nxres vddd suspend wakeup gpio_0 gpio_1 gpio_2 / scb0_1 gpio_3 / scb0_2 gpio_4 / scb0_3 gpio_9 / scb0_5 vssa gpio_15 / scb1_5 gpio_16 gpio_5 / scb0_4 gpio_6 gpio_7 gpio_8 / scb0_0 19 1 18 14 15 16 4 24 11 29 27 vssd vssd 17 20 10 28 12 3 32 2 13 31 30 25 26 gpio_10 / scb1_0 gpio_11 / scb1_1 gpio_12 / scb1_2 gpio_13 / scb1_3 gpio_14 / scb1_4 7 6 8 8 gpio_17 21 gpio_18 22 5 note 4. 1.71 v ? vddd ? 1.89 v - short vccd pin with vddd pin; vddd > 2 v - connect a 1-f decoupling capacitor to the vccd pin.
cy7c65215 document number: 001-81006 rev. *g page 19 of 31 application examples the following section provides cy7c65215 application examples. usb-to-dual uart bridge with battery-charge detection cy7c65215 can connect any embedded system, with a serial port, to a host pc through usb. cy7c65215 enumerates as a dual com port on the host pc. suspend is connected to the mcu to indicate usb suspend or usb unconfigured and the wakeup pin is used to wake up cy7c65215, which in turn issues a remote wakeup to the usb host. gpio1 and gpio0 are configured as rxled# and txled# to drive two leds indicating data receive and transmit respectively. cy7c65215 implements the batter y charger detection function- ality based on the usb battery charging specification rev 1.2. battery-operated bus power syst ems must comply with the following conditions: the system can be powered from the battery (if not discharged) and be operational if vbus is not connected or powered down. the system should not draw more than 100 ma from the vbus prior to usb enumeration and usb suspend mode. the system should not draw more than 500 ma for sdp and 1.5 a for cdp/dcp to comply with the first requirement, vbus from the usb host is connected to the battery charger as well as cy7c65215 as shown in figure 7 . when vbus is connected, cy7c65215 initiates battery charger detectio n and indicates the type of usb charger over bcd0 and bcd1. if the usb charger is sdp or cdp, cy7c65215 enables a 1.5-k pull-up resistor on the usbdp for full-speed enumeration. when vbus is discon- nected cy7c65215 indicates absence of the usb charger over bcd0 and bcd1, and removes the 1.5-k pull-up resistor on usbdp. removing this resistor ensures no current flows from the supply to the usb host through the usbdp, to comply with the usb 2.0 specification. to comply with the second and third requirements, two signals (bcd0 and bcd1) are configured over gpio to communicate the type of usb host charger and the amount of current it can draw from the battery charger. the bcd0 and bcd1 signals can be configured using the configuration utility. figure 7. usb to dual uart brid ge with battery charge detection [5] bat sys 4.7k usb connector vbus d+ d- gnd 0.1 uf 4.7k bcd0 bcd1 mcu vcc txd cts# rts# rxd i/o gnd i/o en2 in en1 battery charger (max8856) vbus usbdp usbdm vddd 19 1 14 15 vccd 1 uf vssd suspend wakeup gpio_3 / scb0_2 gpio_4 / scb0_3 gpio_18 vssa gpio_16 gpio_5 / scb0_4 gpio_8 / scb0_0 16 4 24 12 29 vssd vssd 17 20 13 28 11 22 30 cy7c65215 rxd_0 txd_0 cts#_0 rts#_0 2 rs232 level convertor rtsin ctsout txdin rxdout rtsout ctsin txdout rxdin gpio_12 / scb1_2 gpio_13 / scb1_3 gpio_11 / scb1_1 gpio_10 / scb1_0 8 7 5 6 rxd_1 txd_1 cts#_1 rts#_1 1k rxled# txled# 1k vcc vcc gpio_1 gpio_0 26 25 nxres 18 ovp busdetect b a gpio_17 21 note 5. add a 100 k pull-down resistor on the v bus pin for quick discharge.
cy7c65215 document number: 001-81006 rev. *g page 20 of 31 in a battery charger system.a 9-v spike on the vbus is possible. the cy7c65215 vbus pin is intolerant to volt age above 6 v. in t he absence of over-voltage protection (ovp) on the vbus line, vbus should be connect ed to busdetect (gpio configured) using the resistive network and the out put of battery charger to th e vbus pin of cy7c65215, as shown in the following figure. when vbus and vddd are at the same voltage potential, vbus can be connected to gpio using a series resistor (rs). this is shown in figure 8 . if there is a charger failure and vbus becomes 9 v, then the 10-k ? resistor plays two roles. it reduces the amount of current flowing into the forward biased diodes in the gpio, and it reduces the voltage seen on the pad. figure 8. gpio vbus detection, vbus = vddd when vbus > vddd, a resistor voltage divider is necessary to reduce the voltage from vbus down to vddd for the gpio sensing the vbus voltage. this is shown in the following figure. the resistors should be sized as follows: r1 >= 10 k r2 / (r1 + r2) = vddd / vbus the first condition limits the vo ltage and current for the charger failure situation, as described in the previous paragraph, while the second condition allows for normal-operation vbus detection. figure 9. gpio vbus detection, vbus > vddd b battery charger bat sys cy7c65215 vbus gpio busdetect rs a b a r1 b a r2 vbus = vddd vbus > vddd r1 10 k r2/(r1+r2) = vddd/vbus rs = 10 k vbus rs vbus vddd busdetect cy7c65215 r1 vbus r2 vddd cy7c65215 busdetect
cy7c65215 document number: 001-81006 rev. *g page 21 of 31 capsense in figure 10 cy7c65215 is configured to support six capsense buttons. three gpios (csout 0, csout1, and csout2) are configured to indicate which capsense button is pressed by the finger. it also implements a 2-pin uart on scb0 and a 4-pin uart on scb1. a 2.2-nf (10%) capacitor (cmod) must be connected on the gpio_0 pin for proper capsense operation. optionally, the gpio_7 pin is configured as cshi eld and connected to the shield of the capsense button as shown in figure 10 . the shield prevents false triggering of buttons due to water droplets and guarantees capsense operation (sensors respond to finger touch). for further information on capsense, refer to getting started with capsense . figure 10. capsense schematic usb connector vbus d+ d- gnd 0.1 uf mcu vcc txd rxd i/o i/o vbus usbdp usbdm vddd 19 1 14 15 vccd 1 uf vssd suspend wakeup gpio_3 / scb0_2 gpio_4 / scb0_3 gpio_18 vssa gpio_16 gpio_5 / scb0_4 gpio_8 / scb0_0 16 4 24 12 29 vssd vssd 17 20 13 28 11 22 30 cy7c65215 rxd_0 txd_0 2 rs232 level convertor rtsin ctsout txdin rxdout rtsout ctsin txdout rxdin gpio_12 / scb1_2 gpio_13 / scb1_3 gpio_11 / scb1_1 gpio_10 / scb1_0 8 7 5 6 rxd_1 txd_1 cts#_1 rts#_1 1k vcc gpio_1 gpio_0 26 25 nxres 18 cmod 2.2 nf gpio_2 / scb0_1 27 gpio_6 gpio_7 32 31 gpio_9 / scb0_5 3 gpio_15 / scb1_5 10 gpio_14 / scb1_4 9 gpio_17 21 cshield 560r cs2 560r cs4 560r cs5 560r cs3 1 2 3 csout0 csout1 csout2 i/o i/o i/o 560r cs1 560r cs0 jumper to select shield or no shield vddd 23 csout2 ? csout1 ? csout0 ? capsense ? button ? 0 ? 0 ? 0 ? no ? button ? pressed ? 0 ? 0 ? 1 ? cs0 ? 0 ? 1 ? 0 ? cs1 ? 0 ? 1 ? 1 ? cs2 ? 1 ? 0 ? 0 ? cs3 ? 1 ? 0 ? 1 ? cs4 ? 1 ? 1 ? 0 ? cs5 ? ?
cy7c65215 document number: 001-81006 rev. *g page 22 of 31 usb-to-dual channel (i2c/spi) bridge in figure 11 , cy7c65215 is configured as a usb-to-dual channel (i2c/ spi) bridge. gpio1 and gpio0 are configured as rxled# and txled# to drive two leds indicating data usb receive and transmit respectively. figure 11. usb to i2c/spi bridge i2c the cy7c65215 i2c can be configured as a master or slave using the configuration utility. cy7c65215 supports i2c data rates up to 100 kbits/s in the standard mode (sm) and 400 kbits/s in the fast mode (fm). in the master mode, scl is output from cy7c65215. in the slave mode, scl is input to cy7c65215. the i2c slave address for cy7c65215 can be configured us ing the configuration utility. the sda data line is bi-directional in the master and slave modes. the drive modes of the scl and sda port pins are always open drain. refer to the nxp i2c specificatio n for further details on protocol. spi the cy7c65215 spi can be configured as a master or slave using the configuration utilit y. cy7c65215 supports spi frequency up to 3 mhz. it can support transaction sizes ranging from 4 bits to 16 bits, which can be configured using the config- uration utility. in the master mode, sclk, mosi and ssel lines act as output and miso acts as an input. in the slave mode, scl sclk, mosi, and ssel lines act as input an d miso acts as an output. cy7c65215 supports three versions of the spi protocol: motorola - this is the original spi protocol. texas instruments - a variation of the original spi protocol in which data frames are identified by a pulse on the ssel line. national semiconductors - a half-duplex variation of the original spi protocol. usb connector vbus d+ d- gnd 0.1 uf i2c master/slave 1k rxled# txled# 1k vddd vddd vbus vccd 1 uf cy7c65215 usbdp usbdm vssd nxres vddd gpio_3 / scb0_2 gpio_4 / scb0_3 vssa 19 1 18 14 15 16 4 24 29 vssd vssd 17 20 28 sda scl gpio_1 gpio_0 26 25 2.2k 2.2k vddd 1 2 3 1.8/3.3 v jumper to select 1.8 v/3.3 v or 5 v vcc vin gnd shdn vout vadj jumper to select 1.8 v or 3.3 v vbus 0.1 uf tc 1070 1uf 1m 1 2 3 562k 2m 3.3 v 1.8 v 1.8/3.3 v spi master/slave gpio_10 / scb1_0 gpio_11 / scb1_1 6 5 10k vddd gpio_12 / scb1_2 gpio_13 / scb1_3 7 8 ssel miso mosi sclk vcc gnd gnd
cy7c65215 document number: 001-81006 rev. *g page 23 of 31 motorola the original spi protocol is defined by motorola. it is a full-duplex protocol: transmission and reception occur at the same time. a single (full-duplex) data transfer follows these steps: the master selects a slave by driving its ssel line to '0'. next, it drives data on its mosi line and it drives a clock on its sclk line. the slave uses the edges of the transmitted clock to capture the data on the mosi line. the slave drives data on its miso line. the master captures the data on the miso line. the process is repeated for all the bits in the data transfer. multiple data transfers may happen without the ssel line changing from '0' to '1' and back from '1' to '0' in between the individual transfers. as a result, slaves must keep track of the progress of data transfers to separate individual transfers. when not transmitting data, the ssel line is '1' and sclk is typically off. the motorola spi protocol has four different modes that determine how data is driven and captured on the mosi and miso lines. these modes are determined by clock polarity (cpol) and clock phase (cpha). clock polarity determines the value of the sclk line when not transmitting data: cpol is '0': sclk is '0' when not transmitting data. cpol is '1': sclk is '1' when not transmitting data. clock phase determines when data is driven and capt ured. it is dependent on the value of cpol: figure 12. driving and capturing of mosi/miso data as a function of cpol and cpha table 17. spi protocol modes mode cpol cpha description 0 0 0 data is driven on a falling edge of sclk. data is captured on a rising edge of sclk 1 0 1 data is driven on a rising edge of sclk. data is captured on a falling edge of sclk 2 1 0 data is driven on a rising edge of sclk. data is captured on a falling edge of sclk 3 1 1 data is driven on a falling edge of sclk. data is captured on a rising edge of sclk cpol: ?0?, cpha: ?0? legend: cpol: clock polarity cpha: clock phase sclk: spi interface clock mosi: spi master out / slave in miso: spi master in / slave out sclk mosi/miso cpol: ?0?, cpha: ?1? sclk mosi/miso cpol: ?1?, cpha: ?0? mosi/miso sclk cpol: ?1?, cpha: ?0? mosi/miso sclk msb msb msb msb lsb lsb lsb lsb
cy7c65215 document number: 001-81006 rev. *g page 24 of 31 figure 13. single 8-bit data transfer and two successive 8- bit data transfers in mode 0 (cpol is ?0?, cpha is ?0?) cpol: ?0?, cpha: ?0?, single data transfer sclk ssel mosi msb lsb cpol: ?0?, cpha: ?0?, two successive data transfers sclk ssel mosi msb lsb msb lsb legend: cpol: clock polarity cpha: clock phase sclk: spi interface clock ssel: spi slave select mosi: spi master out / slave in miso: spi master in / slave out miso msb lsb miso msb lsb msb lsb
cy7c65215 document number: 001-81006 rev. *g page 25 of 31 texas instruments the texas instruments' spi protocol redefines the use of the ssel signal. it uses the signal to indicate the start of a data transfer, rather than a low, active slave-select signal. the start of a transfer is indicated by a high, active pulse of a single-bit transfer period. this pulse may occur one cycle before the trans- mission of the first data bit, or may coincide with the transmission of the first data bit. the transmitted clock sclk is a free-running clock. the ti spi protocol only supports mode 1 (cpol is '0' and cpha is '1'): data is driven on a rising edge of sclk and data is captured on a falling edge of sclk. the following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. the ssel pulse precedes the first data bit. note how the ssel pulse of the second data transfer coincides with the last da ta bit of the first data transfer. the following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. the ssel pulse coincides with the first data bit. single data transfer sclk ssel mosi msb lsb two successive data transfers sclk ssel mosi msb lsb msb lsb legend: sclk: spi interface clock ssel: spi slave select pulse mosi: spi master out / slave in miso: spi master in / slave out miso msb lsb miso msb lsb msb lsb single data transfer sclk ssel mosi msb lsb two successive data transfers sclk ssel mosi msb lsb msb lsb legend: sclk: spi interface clock ssel: spi slave select pulse mosi: spi master out / slave in miso: spi master in / slave out miso msb lsb miso msb lsb msb lsb
cy7c65215 document number: 001-81006 rev. *g page 26 of 31 national semiconductors the national semiconductors' spi protocol is a half-duplex protocol. rather than transmission and reception occurring at the same time, transmission and reception take turns (trans- mission happens before reception). a single ?idle? bit transfer period separates transm ission from reception. note: successive data transfers are not separated by an ?idle? bit transfer period. the transmission data transfer size and reception data transfer size may differ. the national semiconductors' spi protocol only supports mode 0: data is driven on a falling edge of sclk and data is captured on a rising edge of sclk. the following figure illustrates a single data transfer and two successive data transfers. in bo th cases, the transmission data transfer size is 8 bits and the reception transfer size is 4 bits. the above figure defines miso and mosi as undefined when the lines are considered idle ( not carrying valid information). it will drive the outgoing line values to '0' during idle time (to satisfy the requirements of specific ma ster devices (nxp lpc17xx) and specific slave devices (microchip eeprom)). legend: sclk: spi interface clock ssel: spi slave select mosi: spi master out / slave in miso: spi master in / slave out single data transfer sclk ssel mosi msb lsb miso msb lsb two successive data transfers sclk ssel mosi msb lsb miso msb lsb ?idle? ?0? cycle msb ?idle? ?0? cycle no ?idle? cycle
cy7c65215 document number: 001-81006 rev. *g page 27 of 31 ordering information ta b l e 1 8 lists the cy7c65215 key package features and ordering codes. for more information, contact your local sales representative. ordering code definitions table 18. key features and ordering information package ordering code operating range 32-pin qfn (5 5 1 mm, 0.5 mm pitch) (pb-free) CY7C65215-32LTXI industrial 32-pin qfn (5 5 1 mm, 0.5 mm pitch) (pb-free) ? tape and reel CY7C65215-32LTXIt industrial x = blank or t blank = tube; t = tape and reel temperature range: i = industrial pb-free package type: lt = qfn number of pins: 32 pins part number family code: 65 = usb hubs technology code: c = cmos marketing code: 7 = cypress products company id: cy = cypress c cy 65 i -32 x 215 7 lt x
cy7c65215 document number: 001-81006 rev. *g page 28 of 31 package information the package currently planned to be supported is the 32-pin qfn. figure 14. 32-pin qfn 5 5 1.0 mm lt32b 3.5 3.5 epad (sawn) 001-30999 *d table 19. package characteristics parameter description min typ max units t a operating ambient temperature ?40 25 85 c thj package ? ja ? 19 ? c/w table 20. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 32-pin qfn 260 c 30 seconds table 21. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 32-pin qfn msl 3
cy7c65215 document number: 001-81006 rev. *g page 29 of 31 acronyms document conventions units of measure table 22. acronyms used in this document acronym description bcd battery charger detection cdc communication driver class cdp charging downstream port dcp dedicated charging port dll dynamic link library esd electrostatic discharge gpio general purpose input/output hbm human-body model i 2 c inter-integrated circuit mcu microcontroller unit osc oscillator phdc personal health care device class pid product identification scb serial communication block scl i2c serial clock sda i2c serial data sdp standard downstream port sie serial interface engine spi serial peripheral interface vcom virtual communication port usb universal serial bus uart universal asynchronous receiver transmitter vid vendor identification table 23. units of measure symbol unit of measure ? c degree celsius dmips dhrystone million instructions per second k ? kilo-ohm kb kilobyte khz kilohertz kv kilovolt mbps megabits per second mhz megahertz mm millimeter vvolt
cy7c65215 document number: 001-81006 rev. *g page 30 of 31 document history page document title: cy7c65215 usb-serial dual channel (uart/i 2 c/spi) bridge with capsense ? and bcd document number: 001-81006 revision ecn orig. of change submission date description of change *g 4287738 samt 02/21/2014 updated ordering information (updated part numbers).
document number: 001-81006 rev. *g revised february 21, 2014 page 31 of 31 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c65215 ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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